%FILENAME%
vtr-8.0.0-4-x86_64.pkg.tar.zst

%NAME%
vtr

%BASE%
vtr

%VERSION%
8.0.0-4

%DESC%
Verilog to Routing -- Open Source CAD Flow for FPGA Research

%CSIZE%
6525293

%ISIZE%
20454327

%MD5SUM%
b1c9e264e765bb9e496a87906ac243a5

%SHA256SUM%
9faba96d6ecb95d5e5af5e542690f0075d0bc57d1f046b13562de7f167e4792e

%PGPSIG%
iQJIBAABCAAyFiEE6HyevZCe8oInuRJWULwdtYO3lwYFAmZCZ6cUHGFzbWVyb25AdWJsaW51eC5jb20ACgkQULwdtYO3lwaw/xAAnuUYiKgHtk9cqTaGu14a/4QJMXBhMEI85jE6yARdKDQ4bPnoAUtaaaKr8PkVaMgmuAO1Bk8XxleKX8M72T0dZPXCTF/uogNsmB0/lZVi2TIXQhte0xdR2Dk3U7Nedo7Ewcj4/9JttSl7rtLRbhY8frCcq2tQHBE1YP6vVXkxx6zsTOcUok04JRyHj514TT01HT3IhdvA2prABqctBb+sLwl0Cw5l6ljAWz1TjgCANU0RTSrmzOdWQlVyrdcOBvWRI8gvnm7naiVRoT2pwJOXUbA0Ez3uMHnNj0JdbR10xp5WFicSnmOHtKqXyGtyT622jauUIOin9pXP8bOIusgLYoHzQFFuEhen4CsYjdRLtyjvTYO7rtIiDdZ5Fn+BVTAwfAyRKMxugpDXX9/jMVyEgOEbnr6N+lrw96oK4oQ33nknLqby5ayW3jXuNU+ODx9uZR/Pn2JCOpKwK0HNs2L1/NRLiSSFHR6sVDxyxvwW0gR/PNFVSxKfnqiDImJCV8P1aLHyJ1s8a8kp5c2k9oBQYHk/sQAqtLVdF0mb2jBwTe6LCqh8q+lB20gm4HTYLHuiEvjfgvHQn6WeTfvBysZPS0AGSfxP88suOmgVQ2YWvv5qpv2tGWVSOmfFHwXpz81h3ndwOSL51K/rd61JR3+R67FC5yno4FiKSBQPllYEzRo=

%URL%
https://verilogtorouting.org

%LICENSE%
MIT

%ARCH%
x86_64

%BUILDDATE%
1637948324

%PACKAGER%
Antonio Rojas <arojas@archlinux.org>

%DEPENDS%
ctags
tbb

%MAKEDEPENDS%
cmake

